k4s560832d cmos sdram rev. 0.0 may. 2002 256mbit sdram 8m x 8bit x 4 banks synchronous dram lvttl revision 0.0 may. 2002 * samsung electronics reserves the right to change products or specification without notice.
k4s560832d cmos sdram rev. 0.0 may. 2002 revision history revision 0.0 (may. , 2002)
k4s560832d cmos sdram rev. 0.0 may. 2002 the k4s560832d is 268,435,456 bits synchronous high data rate dynamic ram organized as 4 x 8,392,608 words by 8bits, fabri- cated with samsung ' s high performance cmos technology. syn- chronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system appli- cations. ? jedec standard 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation ? dqm for masking ? auto & self refresh ? 64ms refresh period (8k cycle) general description features functional block diagram 8m x 8bit x 4 banks synchronous dram ordering information part no. max freq. interface package k4s560832d-nc/l7c 133mhz(cl=2) lvttl 54pin stsop(ii) k4s560832d-nc/l75 133mhz(cl=3) k4s560832d-nc/l1h 100mhz(cl=2) k4s560832d-nc/l1l 100mhz(cl=3) bank select data input register 8m x 8 8m x 8 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we l(u)dqm lwe ldqm dqi clk add lcas lwcbr 8m x 8 8m x 8 timing register * samsung electronics reserves the right to change products or specification without notice.
k4s560832d cmos sdram rev. 0.0 may. 2002 pin configuration (top view) pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a 0 ~ a 12 address row/column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 12 , column address : ca 0 ~ ca 9 ba 0 ~ ba 1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. dq 0 ~ 7 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity. n.c/rfu no connection /reserved for future use this pin is recommended to be left no connection on the device. vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq a3 a1 a0 ap/a10 ba1 ba0 nc nc ras vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq a4 a7 a9 a11 cke nc nc vss vdd we cas cs a2 vss dqm clk a12 a8 a6 a5 1 54 pin stsop(ii) 300mil x 551mil 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 42 41 40 39 38 37 36 35 34 33 32 31 28 29 30 43 44 45 46 47 48 (0.5 mm pin pitch) 49 50 51 52 53 54 bank address ba0-ba1 row address a0-a12 auto precharge a10 (7.62mm x 14.00mm)
k4s560832d cmos sdram rev. 0.0 may. 2002 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes : 1. -75/7c only specify a maximum value of 3.5pf 2. -75/7c only specify a maximum value of 3.8pf 3. -75/7c only specify a maximum value of 6.0pf notes : capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref =1.4v 200 mv) pin symbol min max unit note clock c clk 2.5 4.0 pf 1 ras , cas , we , cs , cke, dqm c in 2.5 5.0 pf 2 address c add 2.5 5.0 pf 2 dq 0 ~ dq 15 c out 4.0 6.5 pf 3
k4s560832d cmos sdram rev. 0.0 may. 2002 dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note -7c -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 100 90 90 90 ma 1 precharge standby cur- rent in power-down mode i cc2 p cke v il (max), t cc = 10ns 2 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby cur- rent in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 6 ma i cc3 ps cke & clk v il (max), t cc = 6 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 30 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 25 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated. t ccd = 2clks 110 110 100 100 ma 1 refresh current i cc5 t rc 3 t rc (min) 220 200 190 190 ma 2 self refresh current i cc6 cke 0.2v c 3 ma 3 l 1 ma 4 1. measured with outputs open. 2. refresh period is 64ms. 3. k4s560832d-nc** 4. k4s560832d-nl** 5. unless otherwise noticed, input swing level is cmos(v ih /v il =v ddq /v ssq ). notes :
k4s560832d cmos sdram rev. 0.0 may. 2002 ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note -7c -75 -1h -1l row active to row active delay t rrd (min) 15 15 20 20 ns 1 ras to cas delay t rcd (min) 15 20 20 20 ns 1 row precharge time t rp (min) 15 20 20 20 ns 1 row active time t ras (min) 45 45 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 60 65 70 70 ns 1 last data in to row precharge t rdl (min) 2 clk 2, 5 last data in to active delay t dal (min) 2 clk + trp - 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp. notes :
k4s560832d cmos sdram rev. 0.0 may. 2002 dq buffer output drive characteristics parameter symbol condition min typ max unit notes output rise time trh measure in linear region : 1.2v ~ 1.8v 1.37 4.37 volts/ns 3 output fall time tfh measure in linear region : 1.2v ~ 1.8v 1.30 3.8 volts/ns 3 output rise time trh measure in linear region : 1.2v ~ 1.8v 2.8 3.9 5.6 volts/ns 1,2 output fall time tfh measure in linear region : 1.2v ~ 1.8v 2.0 2.9 5.0 volts/ns 1,2 1. rise time specification based on 0pf + 50 w to v ss , use these values to design to. 2. fall time specification based on 0pf + 50 w to v dd , use these values to design to. 3. measured into 50pf only, use these values to characterize to. 4. all measurements done with respect to v ss . notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -7c -75 -1h -1l unit note min max min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 7.5 10 10 12 clk to valid output delay cas latency=3 t sac 5.4 5.4 6 6 ns 1,2 cas latency=2 5.4 6 6 7 output data hold time cas latency=3 t oh 3 3 3 3 ns 2 cas latency=2 3 3 3 3 clk high pulse width t ch 2.5 2.5 3 3 ns 3 clk low pulse width t cl 2.5 2.5 3 3 ns 3 input setup time t ss 1.5 1.5 2 2 ns 3 input hold time t sh 0.8 0.8 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 5.4 6 6 ns cas latency=2 5.4 6 6 7 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes :
k4s560832d cmos sdram rev. 0.0 may. 2002 simplified truth table (v=valid, x=don ' t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 12, a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h notes : x 1. op code : operand code a 0 ~ a 11, a 12 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2)
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